ESP8266

Boots real firmware on a from-scratch Tensilica Xtensa LX106 interpreter. The ESP8266 is a single-core LX106 — a cut-down Xtensa that is CALL0-only (no register windows), so code uses the plain CALL0 ABI (a0-a15, call0/callx0/ret). The core implements the 24-bit and 16-bit (density) encodings, the ALU / SAR shift / load-store / branch set, L32R literal loads, the 16-bit and 32-bit multiplies (MUL16/MULL), the normalize (NSA/NSAU) and unaligned-access (SSA8L) ops, and the special registers (SAR, PS, EPC1/EXCCAUSE) via RSR/WSR/XSR. It is wired to an ESP8266 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40100000 / DRAM 0x3FFE8000), the cache-mapped SPI flash (0x40200000), the eFuse block, the FRC timers + WDEV microsecond timer, the GPIO block (on-board LED on GPIO2, 0x60000300), and UART0 (the serial console, 0x60000000). The default is stock, unmodified MicroPython v1.23.0 (MIT): the emulator HLE-s the ESP8266 mask ROM (from the public eagle.rom.addr.v6.ld addresses) and boots the real NONOS SDK all the way through RF/clock bring-up and the os_task loop to a live Python >>> REPL over UART0 — it auto-runs print(2+2) -> 4 and 6*7 -> 42 the moment it comes up, and you can type more (integer/float math, assign variables, print). Also in the picker: an original CC0 bare-metal mini-REPL, Blink (toggles GPIO2), and Hello UART (streams a counter). Open the debugger to single-step the Xtensa core, read/write the a0-a15 registers + PC + SAR/PS/EPC1/EXCCAUSE, disassemble IRAM and flash with the shared from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP8266 memory map. WiFi has no radio here: its register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare module has no on-board audio, so this emulator is silent. Honest limits: WiFi/BLE are RAM-backed stubs (no RF), and timing is instruction-approximate, not cycle-exact.

Boots real firmware on a from-scratch Tensilica Xtensa LX106 interpreter. The ESP8266 is a single-core LX106 — a cut-down Xtensa that is CALL0-only (no register windows), so code uses the plain CALL0 ABI (a0-a15, call0/callx0/ret). The core implements the 24-bit and 16-bit (density) encodings, the ALU / SAR shift / load-store / branch set, L32R literal loads, the 16-bit and 32-bit multiplies (MUL16/MULL), the normalize (NSA/NSAU) and unaligned-access (SSA8L) ops, and the special registers (SAR, PS, EPC1/EXCCAUSE) via RSR/WSR/XSR. It is wired to an ESP8266 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40100000 / DRAM 0x3FFE8000), the cache-mapped SPI flash (0x40200000), the eFuse block, the FRC timers + WDEV microsecond timer, the GPIO block (on-board LED on GPIO2, 0x60000300), and UART0 (the serial console, 0x60000000). The default is stock, unmodified MicroPython v1.23.0 (MIT): the emulator HLE-s the ESP8266 mask ROM (from the public eagle.rom.addr.v6.ld addresses) and boots the real NONOS SDK all the way through RF/clock bring-up and the os_task loop to a live Python >>> REPL over UART0 — it auto-runs print(2+2) -> 4 and 6*7 -> 42 the moment it comes up, and you can type more (integer/float math, assign variables, print). Also in the picker: an original CC0 bare-metal mini-REPL, Blink (toggles GPIO2), and Hello UART (streams a counter). Open the debugger to single-step the Xtensa core, read/write the a0-a15 registers + PC + SAR/PS/EPC1/EXCCAUSE, disassemble IRAM and flash with the shared from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP8266 memory map. WiFi has no radio here: its register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare module has no on-board audio, so this emulator is silent. Honest limits: WiFi/BLE are RAM-backed stubs (no RF), and timing is instruction-approximate, not cycle-exact.

Boots real firmware on a from-scratch Tensilica Xtensa LX106 interpreter. The ESP8266 is a single-core LX106 — a cut-down Xtensa that is CALL0-only (no register windows), so code uses the plain CALL0 ABI (a0-a15, call0/callx0/ret). The core implements the 24-bit and 16-bit (density) encodings, the ALU / SAR shift / load-store / branch set, L32R literal loads, the 16-bit and 32-bit multiplies (MUL16/MULL), the normalize (NSA/NSAU) and unaligned-access (SSA8L) ops, and the special registers (SAR, PS, EPC1/EXCCAUSE) via RSR/WSR/XSR. It is wired to an ESP8266 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40100000 / DRAM 0x3FFE8000), the cache-mapped SPI flash (0x40200000), the eFuse block, the FRC timers + WDEV microsecond timer, the GPIO block (on-board LED on GPIO2, 0x60000300), and UART0 (the serial console, 0x60000000). The default is stock, unmodified MicroPython v1.23.0 (MIT): the emulator HLE-s the ESP8266 mask ROM (from the public eagle.rom.addr.v6.ld addresses) and boots the real NONOS SDK all the way through RF/clock bring-up and the os_task loop to a live Python >>> REPL over UART0 — it auto-runs print(2+2) -> 4 and 6*7 -> 42 the moment it comes up, and you can type more (integer/float math, assign variables, print). Also in the picker: an original CC0 bare-metal mini-REPL, Blink (toggles GPIO2), and Hello UART (streams a counter). Open the debugger to single-step the Xtensa core, read/write the a0-a15 registers + PC + SAR/PS/EPC1/EXCCAUSE, disassemble IRAM and flash with the shared from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP8266 memory map. WiFi has no radio here: its register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare module has no on-board audio, so this emulator is silent. Honest limits: WiFi/BLE are RAM-backed stubs (no RF), and timing is instruction-approximate, not cycle-exact.

Boots real firmware on a from-scratch Tensilica Xtensa LX106 interpreter. The ESP8266 is a single-core LX106 — a cut-down Xtensa that is CALL0-only (no register windows), so code uses the plain CALL0 ABI (a0-a15, call0/callx0/ret). The core implements the 24-bit and 16-bit (density) encodings, the ALU / SAR shift / load-store / branch set, L32R literal loads, the 16-bit and 32-bit multiplies (MUL16/MULL), the normalize (NSA/NSAU) and unaligned-access (SSA8L) ops, and the special registers (SAR, PS, EPC1/EXCCAUSE) via RSR/WSR/XSR. It is wired to an ESP8266 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40100000 / DRAM 0x3FFE8000), the cache-mapped SPI flash (0x40200000), the eFuse block, the FRC timers + WDEV microsecond timer, the GPIO block (on-board LED on GPIO2, 0x60000300), and UART0 (the serial console, 0x60000000). The default is stock, unmodified MicroPython v1.23.0 (MIT): the emulator HLE-s the ESP8266 mask ROM (from the public eagle.rom.addr.v6.ld addresses) and boots the real NONOS SDK all the way through RF/clock bring-up and the os_task loop to a live Python >>> REPL over UART0 — it auto-runs print(2+2) -> 4 and 6*7 -> 42 the moment it comes up, and you can type more (integer/float math, assign variables, print). Also in the picker: an original CC0 bare-metal mini-REPL, Blink (toggles GPIO2), and Hello UART (streams a counter). Open the debugger to single-step the Xtensa core, read/write the a0-a15 registers + PC + SAR/PS/EPC1/EXCCAUSE, disassemble IRAM and flash with the shared from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP8266 memory map. WiFi has no radio here: its register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare module has no on-board audio, so this emulator is silent. Honest limits: WiFi/BLE are RAM-backed stubs (no RF), and timing is instruction-approximate, not cycle-exact.