ESP32

Boots real bare-metal ESP32 firmware on a from-scratch Tensilica Xtensa LX6 interpreter — the site's first Xtensa machine. The core implements the windowed AR register file (64 physical registers with WINDOWBASE/WINDOWSTART and the CALL4/8/12 + ENTRY + RETW rotation, plus the CALL0 ABI), the 24-bit and 16-bit (density) encodings, the ALU / SAR shift / load-store / branch set, L32R literal loads, the 32-bit multiply, the special registers (SAR, PS, the LBEG/LEND/LCOUNT zero-overhead loop, EPC1/EXCCAUSE) via RSR/WSR/XSR, and a basic exception entry. It is wired to an ESP32 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40080000 / DRAM 0x3FFB0000), the XIP flash windows, the GPIO block (the on-board LED on GPIO2), and UART0 (the serial console). The default firmware is an interactive mini-REPL: click the panel and type real integer expressions (try print(2+2) then Enter -> 4, or 6*7 -> 42), or led on / led off to flip the on-board LED, or help. Two more firmwares ship in the picker: Blink, which toggles the on-board LED (GPIO2) and logs over UART0, and Hello UART, which streams a counter on UART0 and exercises the register window at boot. Open the debugger to single-step the Xtensa core, read/write the a0-a15 window + PC + SAR/PS/WINDOWBASE/WINDOWSTART + the loop and exception registers, disassemble IRAM and flash with the new from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP32 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare devkit has no on-board audio, so this emulator is silent. Honest limits: this is a bare-metal partial (not the full ESP-IDF/FreeRTOS+WiFi image), single-core (core0 only; core1 is not run), and timing is instruction-approximate.

Boots real bare-metal ESP32 firmware on a from-scratch Tensilica Xtensa LX6 interpreter — the site's first Xtensa machine. The core implements the windowed AR register file (64 physical registers with WINDOWBASE/WINDOWSTART and the CALL4/8/12 + ENTRY + RETW rotation, plus the CALL0 ABI), the 24-bit and 16-bit (density) encodings, the ALU / SAR shift / load-store / branch set, L32R literal loads, the 32-bit multiply, the special registers (SAR, PS, the LBEG/LEND/LCOUNT zero-overhead loop, EPC1/EXCCAUSE) via RSR/WSR/XSR, and a basic exception entry. It is wired to an ESP32 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40080000 / DRAM 0x3FFB0000), the XIP flash windows, the GPIO block (the on-board LED on GPIO2), and UART0 (the serial console). The default firmware is an interactive mini-REPL: click the panel and type real integer expressions (try print(2+2) then Enter -> 4, or 6*7 -> 42), or led on / led off to flip the on-board LED, or help. Two more firmwares ship in the picker: Blink, which toggles the on-board LED (GPIO2) and logs over UART0, and Hello UART, which streams a counter on UART0 and exercises the register window at boot. Open the debugger to single-step the Xtensa core, read/write the a0-a15 window + PC + SAR/PS/WINDOWBASE/WINDOWSTART + the loop and exception registers, disassemble IRAM and flash with the new from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP32 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare devkit has no on-board audio, so this emulator is silent. Honest limits: this is a bare-metal partial (not the full ESP-IDF/FreeRTOS+WiFi image), single-core (core0 only; core1 is not run), and timing is instruction-approximate.

Boots real bare-metal ESP32 firmware on a from-scratch Tensilica Xtensa LX6 interpreter — the site's first Xtensa machine. The core implements the windowed AR register file (64 physical registers with WINDOWBASE/WINDOWSTART and the CALL4/8/12 + ENTRY + RETW rotation, plus the CALL0 ABI), the 24-bit and 16-bit (density) encodings, the ALU / SAR shift / load-store / branch set, L32R literal loads, the 32-bit multiply, the special registers (SAR, PS, the LBEG/LEND/LCOUNT zero-overhead loop, EPC1/EXCCAUSE) via RSR/WSR/XSR, and a basic exception entry. It is wired to an ESP32 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40080000 / DRAM 0x3FFB0000), the XIP flash windows, the GPIO block (the on-board LED on GPIO2), and UART0 (the serial console). The default firmware is an interactive mini-REPL: click the panel and type real integer expressions (try print(2+2) then Enter -> 4, or 6*7 -> 42), or led on / led off to flip the on-board LED, or help. Two more firmwares ship in the picker: Blink, which toggles the on-board LED (GPIO2) and logs over UART0, and Hello UART, which streams a counter on UART0 and exercises the register window at boot. Open the debugger to single-step the Xtensa core, read/write the a0-a15 window + PC + SAR/PS/WINDOWBASE/WINDOWSTART + the loop and exception registers, disassemble IRAM and flash with the new from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP32 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare devkit has no on-board audio, so this emulator is silent. Honest limits: this is a bare-metal partial (not the full ESP-IDF/FreeRTOS+WiFi image), single-core (core0 only; core1 is not run), and timing is instruction-approximate.