ESP32-S3

Boots real bare-metal ESP32-S3 firmware on a from-scratch Tensilica Xtensa LX7 interpreter (adapted from the site's ESP32 LX6 core — the LX7 shares the windowed register file, the 24/16-bit density encodings and L32R, so the CPU is reused and the SoC around it is the ESP32-S3 memory map). The core implements the windowed AR register file (64 physical registers with WINDOWBASE/WINDOWSTART and the CALL4/8/12 + ENTRY + RETW rotation, plus the CALL0 ABI), the ALU / SAR shift / load-store / branch set, L32R literal loads, the 32-bit multiply, the special registers (SAR, PS, the LBEG/LEND/LCOUNT zero-overhead loop, EPC1/EXCCAUSE) via RSR/WSR/XSR, and a basic exception entry. It is wired to an ESP32-S3 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40370000 / DRAM 0x3FC88000), the XIP flash windows (0x42000000 / 0x3C000000), the GPIO block at 0x60004000 with the bank-1 OUT1/ENABLE1 registers, and UART0 at 0x60000000. The on-board surface of an ESP32-S3-DevKitC is the addressable RGB LED — a WS2812 on GPIO48 that the firmware bit-bangs one-wire and the SoC decodes (HIGH-pulse widths -> a 24-bit GRB colour, the same WS2812 edge-decode the site uses for the Circuit Playground Express NeoPixels) — plus the UART0 serial console. The default firmware is an RGB-LED colour cycle; the picker also has an interactive mini-REPL (click the panel and type print(2+2) then Enter -> 4, or 6*7 -> 42, or led on / led off to light the RGB LED, or help), an RGB blink, and a Hello UART that streams a counter and exercises the register window with a windowed CALL4 -> ENTRY -> RETW at boot. Open the debugger to single-step the Xtensa core, read/write the a0-a15 window + PC + SAR/PS/WINDOWBASE/WINDOWSTART + the loop and exception registers, disassemble IRAM and flash with the shared from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP32-S3 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare devkit has no on-board audio, so this emulator is silent. Honest limits: this is a bare-metal partial (not the full ESP-IDF/FreeRTOS+WiFi image), single-core (core0 only; core1 is not run), and timing is instruction-approximate.

Boots real bare-metal ESP32-S3 firmware on a from-scratch Tensilica Xtensa LX7 interpreter (adapted from the site's ESP32 LX6 core — the LX7 shares the windowed register file, the 24/16-bit density encodings and L32R, so the CPU is reused and the SoC around it is the ESP32-S3 memory map). The core implements the windowed AR register file (64 physical registers with WINDOWBASE/WINDOWSTART and the CALL4/8/12 + ENTRY + RETW rotation, plus the CALL0 ABI), the ALU / SAR shift / load-store / branch set, L32R literal loads, the 32-bit multiply, the special registers (SAR, PS, the LBEG/LEND/LCOUNT zero-overhead loop, EPC1/EXCCAUSE) via RSR/WSR/XSR, and a basic exception entry. It is wired to an ESP32-S3 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40370000 / DRAM 0x3FC88000), the XIP flash windows (0x42000000 / 0x3C000000), the GPIO block at 0x60004000 with the bank-1 OUT1/ENABLE1 registers, and UART0 at 0x60000000. The on-board surface of an ESP32-S3-DevKitC is the addressable RGB LED — a WS2812 on GPIO48 that the firmware bit-bangs one-wire and the SoC decodes (HIGH-pulse widths -> a 24-bit GRB colour, the same WS2812 edge-decode the site uses for the Circuit Playground Express NeoPixels) — plus the UART0 serial console. The default firmware is an RGB-LED colour cycle; the picker also has an interactive mini-REPL (click the panel and type print(2+2) then Enter -> 4, or 6*7 -> 42, or led on / led off to light the RGB LED, or help), an RGB blink, and a Hello UART that streams a counter and exercises the register window with a windowed CALL4 -> ENTRY -> RETW at boot. Open the debugger to single-step the Xtensa core, read/write the a0-a15 window + PC + SAR/PS/WINDOWBASE/WINDOWSTART + the loop and exception registers, disassemble IRAM and flash with the shared from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP32-S3 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare devkit has no on-board audio, so this emulator is silent. Honest limits: this is a bare-metal partial (not the full ESP-IDF/FreeRTOS+WiFi image), single-core (core0 only; core1 is not run), and timing is instruction-approximate.

Boots real bare-metal ESP32-S3 firmware on a from-scratch Tensilica Xtensa LX7 interpreter (adapted from the site's ESP32 LX6 core — the LX7 shares the windowed register file, the 24/16-bit density encodings and L32R, so the CPU is reused and the SoC around it is the ESP32-S3 memory map). The core implements the windowed AR register file (64 physical registers with WINDOWBASE/WINDOWSTART and the CALL4/8/12 + ENTRY + RETW rotation, plus the CALL0 ABI), the ALU / SAR shift / load-store / branch set, L32R literal loads, the 32-bit multiply, the special registers (SAR, PS, the LBEG/LEND/LCOUNT zero-overhead loop, EPC1/EXCCAUSE) via RSR/WSR/XSR, and a basic exception entry. It is wired to an ESP32-S3 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40370000 / DRAM 0x3FC88000), the XIP flash windows (0x42000000 / 0x3C000000), the GPIO block at 0x60004000 with the bank-1 OUT1/ENABLE1 registers, and UART0 at 0x60000000. The on-board surface of an ESP32-S3-DevKitC is the addressable RGB LED — a WS2812 on GPIO48 that the firmware bit-bangs one-wire and the SoC decodes (HIGH-pulse widths -> a 24-bit GRB colour, the same WS2812 edge-decode the site uses for the Circuit Playground Express NeoPixels) — plus the UART0 serial console. The default firmware is an RGB-LED colour cycle; the picker also has an interactive mini-REPL (click the panel and type print(2+2) then Enter -> 4, or 6*7 -> 42, or led on / led off to light the RGB LED, or help), an RGB blink, and a Hello UART that streams a counter and exercises the register window with a windowed CALL4 -> ENTRY -> RETW at boot. Open the debugger to single-step the Xtensa core, read/write the a0-a15 window + PC + SAR/PS/WINDOWBASE/WINDOWSTART + the loop and exception registers, disassemble IRAM and flash with the shared from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP32-S3 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare devkit has no on-board audio, so this emulator is silent. Honest limits: this is a bare-metal partial (not the full ESP-IDF/FreeRTOS+WiFi image), single-core (core0 only; core1 is not run), and timing is instruction-approximate.

Boots real bare-metal ESP32-S3 firmware on a from-scratch Tensilica Xtensa LX7 interpreter (adapted from the site's ESP32 LX6 core — the LX7 shares the windowed register file, the 24/16-bit density encodings and L32R, so the CPU is reused and the SoC around it is the ESP32-S3 memory map). The core implements the windowed AR register file (64 physical registers with WINDOWBASE/WINDOWSTART and the CALL4/8/12 + ENTRY + RETW rotation, plus the CALL0 ABI), the ALU / SAR shift / load-store / branch set, L32R literal loads, the 32-bit multiply, the special registers (SAR, PS, the LBEG/LEND/LCOUNT zero-overhead loop, EPC1/EXCCAUSE) via RSR/WSR/XSR, and a basic exception entry. It is wired to an ESP32-S3 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x40370000 / DRAM 0x3FC88000), the XIP flash windows (0x42000000 / 0x3C000000), the GPIO block at 0x60004000 with the bank-1 OUT1/ENABLE1 registers, and UART0 at 0x60000000. The on-board surface of an ESP32-S3-DevKitC is the addressable RGB LED — a WS2812 on GPIO48 that the firmware bit-bangs one-wire and the SoC decodes (HIGH-pulse widths -> a 24-bit GRB colour, the same WS2812 edge-decode the site uses for the Circuit Playground Express NeoPixels) — plus the UART0 serial console. The default firmware is an RGB-LED colour cycle; the picker also has an interactive mini-REPL (click the panel and type print(2+2) then Enter -> 4, or 6*7 -> 42, or led on / led off to light the RGB LED, or help), an RGB blink, and a Hello UART that streams a counter and exercises the register window with a windowed CALL4 -> ENTRY -> RETW at boot. Open the debugger to single-step the Xtensa core, read/write the a0-a15 window + PC + SAR/PS/WINDOWBASE/WINDOWSTART + the loop and exception registers, disassemble IRAM and flash with the shared from-scratch Xtensa decoder, set breakpoints and write-watchpoints over the real ESP32-S3 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running, and the watchdog is fed so nothing resets. On-board only, and the bare devkit has no on-board audio, so this emulator is silent. Honest limits: this is a bare-metal partial (not the full ESP-IDF/FreeRTOS+WiFi image), single-core (core0 only; core1 is not run), and timing is instruction-approximate.