ESP32-C3

Boots real firmware on a from-scratch RISC-V RV32IMC interpreter (RV32I + M mul/div + C compressed, the machine-mode CSRs, traps and a functional interrupt controller) wired to an ESP32-C3 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x4037C000 / DRAM 0x3FC80000), XIP flash + SPI-flash controller, the GPIO block (on-board LED on GPIO8), UART0 (the serial console), the systimer and the INTERRUPT_CORE0 matrix. The default is stock, unmodified MicroPython v1.24.1 (MIT): the emulator HLE-s the ESP32-C3 mask ROM (from public linker-script addresses) and boots the real ESP-IDF + FreeRTOS all the way to a live Python >>> REPL over UART0 — it auto-runs print(2+2) -> 4 and 6*7 -> 42 the moment it comes up, and you can type more (integer/float math, or drive the on-board GPIO8 LED). Also in the picker: an original CC0 bare-metal mini-REPL, Blink (toggles GPIO8), and Hello UART (streams a counter). Open the debugger to single-step the RISC-V core, read/write x0-x31 + pc + the machine CSRs, disassemble IRAM and flash with the shared RISC-V decoder, and set breakpoints / write-watchpoints over the real ESP32-C3 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running. On-board only, and the bare devkit has no on-board audio, so this emulator is silent.

Boots real firmware on a from-scratch RISC-V RV32IMC interpreter (RV32I + M mul/div + C compressed, the machine-mode CSRs, traps and a functional interrupt controller) wired to an ESP32-C3 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x4037C000 / DRAM 0x3FC80000), XIP flash + SPI-flash controller, the GPIO block (on-board LED on GPIO8), UART0 (the serial console), the systimer and the INTERRUPT_CORE0 matrix. The default is stock, unmodified MicroPython v1.24.1 (MIT): the emulator HLE-s the ESP32-C3 mask ROM (from public linker-script addresses) and boots the real ESP-IDF + FreeRTOS all the way to a live Python >>> REPL over UART0 — it auto-runs print(2+2) -> 4 and 6*7 -> 42 the moment it comes up, and you can type more (integer/float math, or drive the on-board GPIO8 LED). Also in the picker: an original CC0 bare-metal mini-REPL, Blink (toggles GPIO8), and Hello UART (streams a counter). Open the debugger to single-step the RISC-V core, read/write x0-x31 + pc + the machine CSRs, disassemble IRAM and flash with the shared RISC-V decoder, and set breakpoints / write-watchpoints over the real ESP32-C3 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running. On-board only, and the bare devkit has no on-board audio, so this emulator is silent.

Boots real firmware on a from-scratch RISC-V RV32IMC interpreter (RV32I + M mul/div + C compressed, the machine-mode CSRs, traps and a functional interrupt controller) wired to an ESP32-C3 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x4037C000 / DRAM 0x3FC80000), XIP flash + SPI-flash controller, the GPIO block (on-board LED on GPIO8), UART0 (the serial console), the systimer and the INTERRUPT_CORE0 matrix. The default is stock, unmodified MicroPython v1.24.1 (MIT): the emulator HLE-s the ESP32-C3 mask ROM (from public linker-script addresses) and boots the real ESP-IDF + FreeRTOS all the way to a live Python >>> REPL over UART0 — it auto-runs print(2+2) -> 4 and 6*7 -> 42 the moment it comes up, and you can type more (integer/float math, or drive the on-board GPIO8 LED). Also in the picker: an original CC0 bare-metal mini-REPL, Blink (toggles GPIO8), and Hello UART (streams a counter). Open the debugger to single-step the RISC-V core, read/write x0-x31 + pc + the machine CSRs, disassemble IRAM and flash with the shared RISC-V decoder, and set breakpoints / write-watchpoints over the real ESP32-C3 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running. On-board only, and the bare devkit has no on-board audio, so this emulator is silent.

Boots real firmware on a from-scratch RISC-V RV32IMC interpreter (RV32I + M mul/div + C compressed, the machine-mode CSRs, traps and a functional interrupt controller) wired to an ESP32-C3 SoC model at the real hardware addresses: the internal SRAM (IRAM 0x4037C000 / DRAM 0x3FC80000), XIP flash + SPI-flash controller, the GPIO block (on-board LED on GPIO8), UART0 (the serial console), the systimer and the INTERRUPT_CORE0 matrix. The default is stock, unmodified MicroPython v1.24.1 (MIT): the emulator HLE-s the ESP32-C3 mask ROM (from public linker-script addresses) and boots the real ESP-IDF + FreeRTOS all the way to a live Python >>> REPL over UART0 — it auto-runs print(2+2) -> 4 and 6*7 -> 42 the moment it comes up, and you can type more (integer/float math, or drive the on-board GPIO8 LED). Also in the picker: an original CC0 bare-metal mini-REPL, Blink (toggles GPIO8), and Hello UART (streams a counter). Open the debugger to single-step the RISC-V core, read/write x0-x31 + pc + the machine CSRs, disassemble IRAM and flash with the shared RISC-V decoder, and set breakpoints / write-watchpoints over the real ESP32-C3 memory map. WiFi and BLE have no radio here: their register windows are HLE stubs so firmware that probes them keeps running. On-board only, and the bare devkit has no on-board audio, so this emulator is silent.