Teensy 4.0
2019 Open source · CC0 On-board only Online
Teensy 4.0 is PJRC's high-performance 2019 microcontroller board, emulated in the browser on a real NXP i.MX RT1062 (a 600 MHz ARM Cortex-M7 with an FPv5 FPU). It boots exactly like the hardware, through the authentic i.MX boot header, then runs REAL compiled firmware on the actual on-chip peripherals: CCM clock gating, the fast GPIO7 port that drives the on-board LED on pin 13, the GPT1 timer, and LPUART6 serial. Because the whole chip is ordinary JavaScript it plugs into the site's shared debugger: the real ARM disassembler, live r0-r15, xPSR and the FPv5 file, side-effect-free memory at the real i.MX RT1062 addresses, single-instruction step, execution breakpoints and write-watchpoints. The bare Teensy has no user input wired to the firmware and no on-board speaker, so it is honestly silent.
Runs on: Web browser
Teensy 4.0 Online Emulator
Play Teensy 4.0 using JavaScript directly in your browser.
Controls
Runs real compiled PJRC Teensy 4.0 firmware on an in-browser NXP i.MX RT1062 (ARM Cortex-M7, 600 MHz, FPv5-SP FPU). The default is "Blink pin 13": a bare-metal C program that gates the GPIO clock in CCM, routes the pin-13 pad to the fast GPIO7 port, configures it as an output and blinks the on-board LED (pin 13 = GPIO7 bit 3, active-high). "Timer Blink (GPT1)" blinks the same LED but times it with the GPT1 general-purpose timer instead of a busy loop — it starts GPT1 and polls the output-compare flag (SR.OF1). "Serial Hello" brings up LPUART6 (Teensy Serial1, TX on pin 1) and prints a greeting to the serial console while blinking the LED each line; "Serial Counter" prints an incrementing counter over LPUART6. All four are original CC0 programs compiled with clang for thumbv7em (Cortex-M7). Open the debugger, or add ?debug, to single-STEP real Thumb-2 instructions from FlexSPI flash at 0x60000000, set PC breakpoints and write watchpoints, and read the ARM registers (r0-r15, xPSR, N/Z/C/V and the FPv5 file s0-s31) and the real i.MX RT1062 memory map live (ITCM 0x00000000, DTCM 0x20000000, OCRAM 0x20200000, FLASH 0x60000000, peripherals). The bare Teensy 4.0 has no user input wired to the firmware and no on-board speaker, so it is honestly silent with no input pad.
Runs real compiled PJRC Teensy 4.0 firmware on an in-browser NXP i.MX RT1062 (ARM Cortex-M7, 600 MHz, FPv5-SP FPU). The default is "Blink pin 13": a bare-metal C program that gates the GPIO clock in CCM, routes the pin-13 pad to the fast GPIO7 port, configures it as an output and blinks the on-board LED (pin 13 = GPIO7 bit 3, active-high). "Timer Blink (GPT1)" blinks the same LED but times it with the GPT1 general-purpose timer instead of a busy loop — it starts GPT1 and polls the output-compare flag (SR.OF1). "Serial Hello" brings up LPUART6 (Teensy Serial1, TX on pin 1) and prints a greeting to the serial console while blinking the LED each line; "Serial Counter" prints an incrementing counter over LPUART6. All four are original CC0 programs compiled with clang for thumbv7em (Cortex-M7). Open the debugger, or add ?debug, to single-STEP real Thumb-2 instructions from FlexSPI flash at 0x60000000, set PC breakpoints and write watchpoints, and read the ARM registers (r0-r15, xPSR, N/Z/C/V and the FPv5 file s0-s31) and the real i.MX RT1062 memory map live (ITCM 0x00000000, DTCM 0x20000000, OCRAM 0x20200000, FLASH 0x60000000, peripherals). The bare Teensy 4.0 has no user input wired to the firmware and no on-board speaker, so it is honestly silent with no input pad.
Runs real compiled PJRC Teensy 4.0 firmware on an in-browser NXP i.MX RT1062 (ARM Cortex-M7, 600 MHz, FPv5-SP FPU). The default is "Blink pin 13": a bare-metal C program that gates the GPIO clock in CCM, routes the pin-13 pad to the fast GPIO7 port, configures it as an output and blinks the on-board LED (pin 13 = GPIO7 bit 3, active-high). "Timer Blink (GPT1)" blinks the same LED but times it with the GPT1 general-purpose timer instead of a busy loop — it starts GPT1 and polls the output-compare flag (SR.OF1). "Serial Hello" brings up LPUART6 (Teensy Serial1, TX on pin 1) and prints a greeting to the serial console while blinking the LED each line; "Serial Counter" prints an incrementing counter over LPUART6. All four are original CC0 programs compiled with clang for thumbv7em (Cortex-M7). Open the debugger, or add ?debug, to single-STEP real Thumb-2 instructions from FlexSPI flash at 0x60000000, set PC breakpoints and write watchpoints, and read the ARM registers (r0-r15, xPSR, N/Z/C/V and the FPv5 file s0-s31) and the real i.MX RT1062 memory map live (ITCM 0x00000000, DTCM 0x20000000, OCRAM 0x20200000, FLASH 0x60000000, peripherals). The bare Teensy 4.0 has no user input wired to the firmware and no on-board speaker, so it is honestly silent with no input pad.
Runs real compiled PJRC Teensy 4.0 firmware on an in-browser NXP i.MX RT1062 (ARM Cortex-M7, 600 MHz, FPv5-SP FPU). The default is "Blink pin 13": a bare-metal C program that gates the GPIO clock in CCM, routes the pin-13 pad to the fast GPIO7 port, configures it as an output and blinks the on-board LED (pin 13 = GPIO7 bit 3, active-high). "Timer Blink (GPT1)" blinks the same LED but times it with the GPT1 general-purpose timer instead of a busy loop — it starts GPT1 and polls the output-compare flag (SR.OF1). "Serial Hello" brings up LPUART6 (Teensy Serial1, TX on pin 1) and prints a greeting to the serial console while blinking the LED each line; "Serial Counter" prints an incrementing counter over LPUART6. All four are original CC0 programs compiled with clang for thumbv7em (Cortex-M7). Open the debugger, or add ?debug, to single-STEP real Thumb-2 instructions from FlexSPI flash at 0x60000000, set PC breakpoints and write watchpoints, and read the ARM registers (r0-r15, xPSR, N/Z/C/V and the FPv5 file s0-s31) and the real i.MX RT1062 memory map live (ITCM 0x00000000, DTCM 0x20000000, OCRAM 0x20200000, FLASH 0x60000000, peripherals). The bare Teensy 4.0 has no user input wired to the firmware and no on-board speaker, so it is honestly silent with no input pad.
Configurations
| Configuration | Emulator | Machine | OS | Legal | |
|---|---|---|---|---|---|
| Blink pin 13 (on-board LED) | Teensy 4.0 | Teensy 4.0 | open | Open ⛶ | |
| Timer Blink (GPT1) | Teensy 4.0 | Teensy 4.0 | open | Open ⛶ | |
| Serial Hello | Teensy 4.0 | Teensy 4.0 | open | Open ⛶ | |
| Serial Counter | Teensy 4.0 | Teensy 4.0 | open | Open ⛶ |
Chips
Notes
Embedding
This is a two-layer stack: a real ARM Cortex-M7 core underneath, and a from-scratch NXP i.MX RT1062 SoC + Teensy 4.0 board on top. It loads real Cortex-M7 FlexSPI flash images and runs them on the actual on-chip peripherals — CCM clock gating, the fast GPIO7 port, LPUART6 and the GPT1 timer — at their real addresses. The firmware is genuine compiled machine code, not a shim.
- The CPU.
cortex-m7.jsexecutes Thumb-2 plus the FPv5-SP VFP. The i.MX RT1062 is a real Cortex-M7 (ARMv7E-M), so it runs the Teensy image directly — the same core the Playdate and NumWorks builds use. - Real i.MX RT boot. The image carries the genuine boot header: a FlexSPI Config Block at
0x60000000and an Image Vector Table (header0x432000D1) at0x60000400whoseentrypoints at the ResetHandler. On reset the board reads the IVT, loadsPCfromentryandSPfrom the top of DTCM — exactly as the boot ROM does on silicon — then the ResetHandler sets VTOR, copies.dataand runsmain(). - The board, in JavaScript.
teensy4-board.jsmaps ITCM/DTCM/OCRAM/FlexSPI-flash and the peripheral block at their real i.MX RT1062 addresses, folds the GPIODR_SET/DR_CLEAR/DR_TOGGLEalias registers intoDR, captures every byte written toLPUART6->DATAinto the serial console, and counts GPT1.
| Piece | Kind | What it does |
|---|---|---|
Teensy4.create(canvas) | factory | Build the ARM core + the i.MX RT1062 memory map + peripherals. |
load(bytes) / reset() | method | Copy the flat image into FLASH; reset parses the IVT and loads PC/SP. |
runFrame() | method | Step ~120k instructions and advance the GPT1 timer. |
ledOn() / getSerial() | method | The on-board LED (pin 13, active-high) state and the accumulated LPUART6 output. |
present() | method | Draw the on-board LED indicator and the serial console to the canvas. |
Debugger integration
teensy4-debug.js reads window.EMU_BOOT and hands the shared debugger a genuine ARM Cortex-M7 machine — the same core the firmware runs on, exposed instruction-accurately.
- Registers.
registers()reads r0-r12, SP, LR, PC, xPSR, the APSR flags N/Z/C/V and the whole FPv5 single-precision file s0-s31 live each refresh; each has aset()that writes straight back into the core's register file. - Disassembly. FLASH is decoded with the shared
cortex-m7decoder (the Thumb-2 disassembler), so the code window shows real ARM mnemonics at the reset address in the FlexSPI XIP region0x60000000. - Single-step. Step calls
transport.stepInsn, which advances the core exactly one Thumb-2 instruction; PC and the registers update after each step. You can watch the ResetHandler set VTOR, copy.datato DTCM and fall intomain(). - Breakpoints & watchpoints. Execution breakpoints are a PC set the run-loop checks before each instruction; write watchpoints wrap the board's memory-write path and pause when a watched address is written (e.g.
GPIO7_DR_SETat0x42004084orLPUART6->DATAat0x4019801C). Both are real. - Memory map. Six chips read the real address space side-effect-free: FLASH (program, disassembled, 0x60000000), ITCM (0x00000000), DTCM (0x20000000), OCRAM (0x20200000), the low AIPS peripherals (CCM/IOMUXC/GPT1/LPUART6) and the fast-GPIO block (0x42000000). Reading the dynamic registers (LPUART STAT, GPIO PSR) is side-effect-free.
Architecture
The PJRC Teensy 4.0 is a small, very fast hobbyist board: an NXP i.MX RT1062 — a 600 MHz ARM Cortex-M7 (ARMv7E-M with the FPv5-SP FPU) with 1 MB tightly-coupled RAM and 2 MB external FlexSPI flash — on a breadboard-friendly PCB with an on-board LED and USB. This build models the chip from scratch on the shared ARM core.
- Cortex-M7 CPU — runs the real Thumb-2 image. ITCM is at
0x00000000, DTCM at0x20000000, OCRAM at0x20200000, the FlexSPI XIP flash at0x60000000, all peripherals from0x40000000. The code executes in place from flash exactly as on the Teensy. - i.MX RT boot header — the FlexSPI Config Block at
0x60000000and the Image Vector Table at0x60000400(header0x432000D1,entry= ResetHandler). The board parses the IVT on reset and boots from it, loading SP from the top of DTCM as the boot ROM does. - CCM (Clock Controller Module,
0x400FC000) — the firmware gates each peripheral's clock through theCCGRregisters before touching it; the board stores them like silicon. - Fast GPIO7 — the high-speed alias the Teensy core uses for the GPIO pins, with
DR,GDIRand the atomicDR_SET/DR_CLEAR/DR_TOGGLEalias registers. The on-board LED is on pin 13 = GPIO7 bit 3 and is active-high: the board lights it when that bit is driven high (whatdigitalWriteFast(13,HIGH)compiles to). - LPUART6 (
0x40198000, Teensy Serial1) — the serial port.STATkeepsTDRE/TCasserted so polling transmit code runs, and every byte written toDATAis captured onto the on-screen serial console (TX on pin 1). - GPT1 (
0x401EC000) — a general-purpose timer with prescaler (PR), output-compare (OCR1), free-running counter (CNT) and the compare flag (SR.OF1), advanced by executed instructions; the Timer Blink program times the LED off GPT1. SysTick and the NVIC come from the core. - Content. Four original CC0 bare-metal C programs compiled with clang for thumbv7em: Blink pin 13, Timer Blink (GPT1), Serial Hello and Serial Counter. No proprietary firmware is used.
- Honest limits. A Teensy 4.0 has no on-board audio (audio needs the separate Audio Shield), so this emulator is genuinely silent with no sound path. It has no user-input peripheral wired to the firmware (the LED is an output and the serial console is TX-only), so there is no input pad. USB, the FlexSPI controller internals, the PLLs, ADC, SPI/I2C, DMA and the interrupt-driven paths are not modelled — only what real blink + serial firmware exercises: the boot IVT, CCM gating, GPIO7, LPUART6 and GPT1. The FlexSPI Config Block is a minimal tag-only placeholder (the flash is mapped directly).