Parallax Propeller 1 (P8X32A)

Embedding

There is no upstream runtime to vendor here — the Propeller 1 is written from scratch as three plain-global JavaScript modules, loaded in order:

// 1. the assembled firmware, 2. the chip core, 3. the debugger plug-in
<script src="firmware.js"></script>      // window.PROP_FW: original CC0 PASM programs, real 32-bit longs
<script src="propeller.js"></script>     // window.Propeller: the P8X32A SoC + 8-LED board
<script src="propeller-debug.js"></script> // EmuKit.defineMachine(...)

Boot. Construct the machine on a <canvas>, load a firmware image (a cog 0 image + a hub image) and run your own loop. One frame is a burst of system ticks — each tick advances the global counter and steps every running cog once — so the debugger can pause and step it:

var chip = new Propeller(canvas, PROP_FW.blink, { speed: 6000 });
(function loop(){
  var hit = chip.run(chip.speed, bps); // bps = breakpoint Set (cog-0 PC)
  chip.render();
  if (!hit) requestAnimationFrame(loop);
})();

The machine is plain objects — no wasm heap — so the debugger reaches everything directly:

Debugger integration

The debugger plug-in (propeller-debug.js) reads window.EMU_BOOT and calls EmuKit.defineMachine. Because the whole machine is ordinary JavaScript, single-stepping is just one stepCog of cog 0, registers are read and written straight off chip.cogs[0] (its PC, the C and Z flags and the special registers PAR/CNT/INA/OUTA/DIRA/CTRA/FRQA/PHSA and the B counterparts), and execution breakpoints are a host-side Set the loop checks against cog 0's program counter. Hub write watchpoints wrap the hub write path and pause when a watched hub byte is written.

A new propeller disassembler (/debugger/src/cpus/propeller.js) decodes the fixed 32-bit Propeller instruction — the 6-bit opcode, the ZCRI effect flags (WZ/WC/WR/I), the 4-bit condition field (every instruction is conditionally executed) and the 9-bit destination and source/immediate — showing the condition prefix (if_z, if_nc, …), the wc/wz effects and the named special registers, so the cog RAM disassembles to real PASM.

Architecture

The Parallax Propeller 1 (P8X32A) is a distinctive multicore microcontroller: eight identical 32-bit processors ("cogs") share a common 32 KB hub RAM through a round-robin "hub" and a set of 32 I/O pins. This emulator is a from-scratch model of the chip:

• Eight cogs — each an independent 32-bit CPU with 512 longs (2 KB) of dual-port cog RAM. Cog 0 boots automatically; the others are launched by COGINIT/COGNEW, which loads a 512-long image out of the hub into a fresh cog.
• The instruction — a fixed 32-bit word: a 6-bit opcode, the ZCRI effect flags, a 4-bit condition field that makes every instruction conditional (executed only when the C/Z flags match, else a NOP), and 9-bit destination and source/immediate fields. The ALU (add/sub, the shifts and rotates, the logic and MUX ops, the compares), the branch family (djnz, tjz, jmp/jmpret) and the waits (waitcnt, waitpeq/waitpne) are implemented.
• Cog special registers — the top 16 longs: PAR, CNT (the shared system counter), INA, OUTA, DIRA, and the two counter modules CTRA/CTRB with their FRQ/PHS accumulators (NCO single-ended mode drives an I/O pin straight from the phase MSB).
• Hub RAM — 32 KB shared between all cogs, reached by the hub ops RDLONG/WRLONG/RDWORD/WRWORD/RDBYTE/WRBYTE and by COGINIT.
• On-board surface — an eight-LED bank on pins P16..P23 (the classic Parallax Propeller Demo Board arrangement), driven by real OUTA/DIRA writes and by the counters. A pin reads high if any running cog drives it high.
• Content — five original CC0 hand-assembled PASM programs: blink one LED, a knight-rider chase, a binary counter, a CTRA/NCO counter-driven blink, and a two-cog demo. No third-party firmware.
• Honest limits. The board has no on-board audio, so this emulator is silent by design. Hub access is modelled as always-available rather than the real 16-clock round-robin hub window (timing is not cycle-accurate: one instruction ≈ one tick, not the real four clocks). The video generators (VGA/composite via WAITVID/VCFG/VSCL), the PLL counter modes, the cog locks and boot-from-EEPROM/SPIN interpreter are stubbed or not modelled. Everything the bundled firmware exercises — full instruction execution with conditional execution and the ZCRI flags, digital I/O, the CTRA/CTRB counters in NCO mode, WAITCNT pacing off the shared counter, and multi-cog launch via COGINIT loading out of hub RAM — is modelled faithfully.