PIC16F84A

Embedding

There is no upstream runtime to vendor here — the PIC16F84A is written from scratch as three plain-global JavaScript modules, loaded in order:

// 1. the assembled firmware, 2. the chip core, 3. the debugger plug-in
<script src="firmware.js"></script>      // window.PIC_FW: original CC0 programs, 14-bit words
<script src="pic16f84a.js"></script>    // window.PIC16F84A: the mid-range PIC chip
<script src="pic16f84a-debug.js"></script> // EmuKit.defineMachine(...)

Boot. Construct the chip on a <canvas>, load a firmware word image and run your own loop. One frame is a burst of instruction cycles; you own it, so the debugger can pause and step it:

var pic = new PIC16F84A(canvas, PIC_FW.blink.words, { speed: 20000 });
(function loop(){
  var hit = pic.run(pic.speed, bps); // bps = breakpoint Set (byte addresses)
  pic.render();
  if (!hit) requestAnimationFrame(loop);
})();

The chip is plain objects — no wasm heap — so the debugger reaches everything directly:

Debugger integration

The debugger plug-in (pic16f84a-debug.js) reads window.EMU_BOOT and calls EmuKit.defineMachine. Because the whole chip is ordinary JavaScript, single-stepping is just pic.stepInsn(), registers are read and written straight off pic.w / pic.ram, and execution breakpoints are a host-side Set the loop checks against the program counter at each instruction boundary. Watchpoints wrap the file-register write path (pic.writeMem) and pause when a watched data address is written.

A new pic disassembler (/debugger/src/cpus/pic.js) decodes the mid-range 14-bit program words — MOVLW, BSF/BCF, GOTO/CALL, DECFSZ, BTFSS and the rest of the 35-instruction set. The flash is presented to the shared views packed two bytes per word (little-endian), so the PC and the breakpoint gutter both use byte addresses (word << 1), like the PDP-8 plug-in.

Architecture

The PIC16F84A is the iconic hobbyist microcontroller — an 18-pin mid-range PIC. This emulator is a from-scratch model of the whole chip:

• Mid-range core — a Harvard machine: 14-bit program words in a 1K flash, separate 8-bit data memory, an 8-bit working register W, a 13-bit program counter and an 8-level hardware call stack. The full 35-instruction set is implemented, cycle-accounted for timer timing.
• File registers — the special-function registers (STATUS, PCL/PCLATH, FSR/INDF indirection, OPTION_REG, INTCON, TMR0) plus 68 bytes of general-purpose RAM, with bank switching through STATUS<RP0>.
• I/O — PORTA (5-bit) and PORTB (8-bit), each with a TRIS direction latch. The on-board LED is wired to RB0; the other pins are shown as indicators. Push buttons on RA0..RA4 drive the input pins.
• TMR0 — the 8-bit timer with its programmable prescaler (1:2 … 1:256 via OPTION_REG), counting the instruction clock and setting T0IF on overflow.
• Interrupts — the single interrupt vector at 0x0004, with GIE / T0IE / INTE / RBIE enables, the matching flags in INTCON, and RETFIE.
• EEPROM — 64 bytes of data EEPROM via EECON1 / EEDATA / EEADR.

Honest limits. The PIC16F84A has no audio hardware, so this emulator is silent by design. The watchdog timer, SLEEP wake-up, the TMR0 write inhibit and the EECON2 unlock sequence are simplified; T0CS external-clock mode has no pin to pulse. Everything the bundled firmware exercises — instruction execution, banking, TMR0 with prescaler, polled and interrupt-driven timing, PORT I/O — is modelled faithfully.