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STM32 Nucleo-F411RE

2014 Open source · CC0 On-board only Online

The STM32 Nucleo-F411RE is STMicroelectronics' popular low-cost developer board — an STM32F411RE (a 100 MHz ARM Cortex-M4F, ARMv7E-M with a single-precision FPU, with 512 KB flash and 128 KB SRAM) with an on-board ST-Link debugger — emulated from scratch in the browser on this site's shared ARM core. It runs REAL compiled firmware: a flat flash image with the ARM vector table at 0x08000000 boots exactly as on silicon (SP and PC loaded from the table), then drives the real STM32F411 registers. The on-board surface a Nucleo actually has is shown — the green user LED LD2 on PA5 (active-high), the blue user button B1 on PC13 (active-low) and a USART2 serial console (the ST-Link virtual COM port) — with nothing invented: no breadboard, no fake audio (a Nucleo has no speaker, so it is honestly silent). Because the whole chip is ordinary JavaScript, it plugs into this site's shared debugger: the real Thumb-2 disassembler, live r0-r15 / xPSR / N-Z-C-V and the FPU s0-s31, side-effect-free FLASH / SRAM / peripheral memory at the real addresses, single-instruction step, execution breakpoints and write-watchpoints.

NUCLEO-F411RE at STMicroelectronics ↗

Runs on: Web browser

STM32 Nucleo-F411RE Online Emulator

Play STM32 Nucleo-F411RE using JavaScript directly in your browser.

Configurations

ConfigurationEmulatorMachineOSLegal
Blink LD2 (on-board LED)STM32 Nucleo-F411RESTM32 Nucleo-F411REopenOpen ⛶
Button toggles LD2STM32 Nucleo-F411RESTM32 Nucleo-F411REopenOpen ⛶
USART2 Serial (ST-Link VCP)STM32 Nucleo-F411RESTM32 Nucleo-F411REopenOpen ⛶
Timer Blink (TIM2)STM32 Nucleo-F411RESTM32 Nucleo-F411REopenOpen ⛶

Chips

Notes

Embedding

This is a two-layer stack: a real ARM CPU core underneath, and a from-scratch STM32F411 SoC + NUCLEO-F411RE board on top. It loads real Cortex-M4 flash images and runs them on the actual on-chip peripherals — RCC clock gating, the GPIO ports, USART2 and the TIM2 timer — at their real addresses. The firmware is genuine compiled machine code, not a shim.

  • The CPU. cortex-m7.js executes Thumb-2 plus the FPv5 VFP. The real chip is a Cortex-M4F (ARMv7E-M with an FPU); this core is the same ARMv7-M family, so it runs the M4 image unchanged.
  • Real reset. The image is a real flash image with the ARM vector table at 0x08000000: on reset the board loads SP from word 0 and PC from word 1, exactly like the silicon.
  • The board, in JavaScript. nucleo-f411-board.js maps FLASH/SRAM/peripherals at their real STM32F411 addresses, answers the RCC clock-ready bits the firmware spins on, folds each GPIO BSRR into ODR, drives the button level into GPIOC->IDR, captures every byte written to USART2->DR into the serial console, and counts TIM2.
PieceKindWhat it does
NucleoF411.create(canvas)factoryBuild the ARM core + the STM32F411 memory map + peripherals.
load(bytes) / reset()methodCopy the flat image into FLASH; reset loads SP/PC from the vector table at 0x08000000.
runFrame()methodStep ~60k instructions and advance the TIM2 timer.
setButton(down)inputDrive the blue user button B1 (PC13) level low while held.
ledOn() / getSerial()methodThe on-board LED (LD2, PA5, active-high) state and the accumulated USART2 output.

Debugger integration

nucleo-f411-debug.js reads window.EMU_BOOT and hands the shared debugger a genuine ARM Cortex-M4F machine — the same core the firmware runs on, exposed instruction-accurately.

  • Registers. registers() reads r0-r12, SP, LR, PC, xPSR and the APSR flags N/Z/C/V live each refresh, plus the FPU single-precision registers s0-s31; r0-r15 and the flags each have a set() that writes straight back into the core's register file.
  • Disassembly. FLASH is decoded with the shared cortex-m7 decoder (the Thumb-2 disassembler), so the code window shows real ARM mnemonics at the real reset address 0x08000000.
  • Single-step. Step calls transport.stepInsn, which advances the core exactly one Thumb instruction; PC and the registers update after each step. You can watch the reset handler copy .data to SRAM and fall into main().
  • Breakpoints & watchpoints. Execution breakpoints are a PC set the run-loop checks before each instruction; write watchpoints wrap the board's memory-write path and pause when a watched address is written (e.g. GPIOA->ODR at 0x40020014 or USART2->DR at 0x40004404). Both are real.
  • Memory map. Three chips read the real address space side-effect-free: FLASH (program, disassembled, 0x08000000), SRAM (0x20000000), and the peripheral block (0x40000000 — TIM2, USART2, GPIOA-C, RCC). Reading the dynamic registers (USART2 SR, GPIO IDR incl. the live button on PC13) is side-effect-free.
  • Input. The blue user button B1 is in the shared Controller panel; pressing it drives GPIOC->IDR bit 13 low, exactly as the hardware button does.

Architecture

The ST NUCLEO-F411RE is STMicroelectronics' popular low-cost developer board built around the STM32F411RE — a 100 MHz ARM Cortex-M4F (ARMv7E-M, with a single-precision FPU) with 512 KB flash and 128 KB SRAM — with an on-board ST-Link debugger/programmer. This build models the chip from scratch on the shared ARM core.

  • Cortex-M4F CPU — runs the real Thumb-2 image. FLASH is at 0x08000000 (the vector table: word0 = initial SP, word1 = reset handler), SRAM at 0x20000000, all peripherals at 0x40000000. On reset SP and PC are loaded from the vector table, exactly as on silicon.
  • RCC (Reset & Clock Control, 0x40023800) — the firmware gates each peripheral's clock through AHB1ENR/APB1ENR/APB2ENR before touching it, and spins on the clock-ready bits (HSIRDY, HSERDY, PLLRDY); the board answers those bits so real clock-setup code proceeds.
  • GPIO ports A/B/C — the STM32F4 MODER mode, PUPDR pull, IDR input, ODR output and the atomic BSRR set/reset register (low 16 bits set, high 16 bits reset). The green user LED LD2 is on PA5 and is active-high (lit when GPIOA->ODR bit 5 is high); the blue user button B1 is on PC13 and is active-low (a pull-up idles it high; pressing pulls GPIOC->IDR bit 13 low).
  • USART2 (0x40004400) — the serial port routed to the ST-Link virtual COM port (TX = PA2). SR keeps TXE/TC asserted so polling transmit code runs, and every byte written to DR is captured onto the on-screen serial console.
  • TIM2 — a general-purpose 32-bit timer used here as 16-bit: prescaler (PSC), auto-reload (ARR), counter (CNT), EGR.UG force-update and the update flag (SR.UIF), advanced by executed instructions; the Timer Blink program times the LED off TIM2. SysTick and the NVIC come from the core.
  • Content. Four original CC0 bare-metal C programs compiled with clang for thumbv7em: Blink LD2, Button toggles LD2, USART2 Serial and Timer Blink (TIM2). No proprietary firmware is used.
  • Honest limits. A Nucleo has no on-board audio (no speaker/DAC), so this emulator is genuinely silent with no sound path. USB, ADC, SPI/I2C, DMA and the interrupt-driven paths of the untouched peripherals are not modelled — the bundled firmware polls.