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Fairchild Channel F

1976 Open source · MIT Online

The Fairchild Channel F (originally the Video Entertainment System) was the first cartridge-based games console, built around the two-chip Fairchild F8 processor. This is an in-browser emulator with a hand-written F8 core that renders the console's 128×64 two-bit playfield to a canvas and plugs into the shared debugger, so you can single-step the F8, set breakpoints and inspect memory. With no cartridge it boots the console's built-in Hockey and Tennis.

Reference emulator ↗

Visit the official site ↗

Runs on: Web browser

Fairchild Channel F Online Emulator

Play Fairchild Channel F using JavaScript directly in your browser.

Configurations

ConfigurationEmulatorMachineOSLegal
Hockey / Tennis (built-in)Fairchild Channel FFairchild Channel FgreyOpen ⛶

Machines emulated

Fairchild Channel F

Chips

Fairchild F8

Notes

Embedding

The Channel F core is a single hand-written JavaScript file, channelf.js, exposing a ChannelF class. Vendor it, load the grey system BIOS, and drive it from a loop you own. The machine has no address bus, so you step it and read its state directly:

var cf = new ChannelF();
var bios = new Uint8Array(await (await fetch(biosUrl)).arrayBuffer());
cf.loadBios(bios);            // 2 KB BIOS -> two 1 KB 3851 PSU pages at $0000/$0400
// cf.loadCart(cartBytes);      // optional Videocart, mapped from $0800
(function loop(){ cf.runFrame(); render(); requestAnimationFrame(loop); })();

The machine is plain JavaScript. Everything the host (or the debugger) needs is a method or field on the instance:

MemberKindWhat it does
step()methodLatch inputs, run the one-pixel video write, then execute one F8 instruction; returns the clock count. The single-step primitive.
runFrame()methodRun ~33,333 clocks (2 MHz / 60 Hz) worth of instructions - one video frame.
reset()methodRestart the CPU at address 0 (the BIOS entry).
readCode(a) / writeData(a,v)methodSide-effect-free byte read of the program/data space; write (only RAM pages take it).
renderInto(buf32)methodPaint the 128×64 field into a 32-bit RGBA buffer, applying the per-row palette.
acc, isar, pc0, pc1, dc0, dc1fieldsThe F8 accumulator, the 6-bit scratchpad pointer ISAR, and the PSU program/data counters, read and pokeable live.
regsfieldThe 64-byte scratchpad register file.
plane0, plane1fieldsThe two VRAM bit-planes (128×64 pixels); together they give each pixel a 2-bit colour.
btnfieldController / console button state (up down left right push pull cw ccw time mode hold start).

Debugger integration

The debugger plug-in (channelf-debug.js) reads the live core each refresh and calls EmuKit.defineMachine. Because the whole machine is ordinary JavaScript, no hooks are needed:

  • CPU decoder. The F8 is not a 6502/Z80, so a new disassembler lives at /debugger/src/cpus/f8.js (registered as f8) - a flat opcode table over the ~90 F8 instructions; unknown bytes decode as .byte.
  • Registers are read from acc / isar / pc0 / pc1 / dc0 / dc1 and the five W-register flags (N C Z O I) each refresh, and written back through the set callbacks.
  • Memory. Three chips: the program/data space (BIOS + cartridge + RAM, disassembled with f8), the 64-byte scratchpad, and the 128×64 2-bit video RAM. Reads are side-effect-free.
  • Single step is one step() (one instruction). Breakpoints compare PC0 against a set before each instruction; watchpoints wrap writeData. Both are host-side, so they cost nothing when the debugger is closed.
  • “PC” is the PSU's PC0 program counter - the F8 keeps the address in the memory chips, not the CPU.

Architecture

The Channel F splits the processor across two chips, an unusual arrangement for 1976:

  • Fairchild F8 (3850) CPU - an 8-bit accumulator, a 64-byte scratchpad addressed by the 6-bit ISAR, and a 5-bit status (W) register. It has no address bus and no stack.
  • 3851 PSU - holds 1 KB of mask ROM and the program counters PC0/PC1 and data counter DC0. The console has two (the BIOS: SL31253 at $0000, SL31254 at $0400); each cartridge adds its own from $0800.
  • Video - a 128×64 static RAM of 2-bit pixels. The CPU sets an X port, a Y port and a 2-bit colour, then pulses port 0 bit 5 to latch one pixel. Two bits per row select that row's background from a four-colour palette.
  • Controllers - the famous plunger: move in four directions, plus push, pull and twist, read as active-low bits multiplexed onto the same ports the video uses.

With no cartridge the BIOS runs its built-in Hockey / Tennis, the deliverable default here. The core faithfully re-implements the F8 arithmetic (including the BCD adjust and the ISAR post-increment/decrement register forms) and the PSU's page/port addressing.