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Zilog Z8000
1979
Zilog's 1979 16-bit CPU. Sixteen 16-bit general registers that also group as sixteen byte registers (RH0–RH7 / RL0–RL7), eight register pairs (RR) and four quads (RQ); a 16-bit FCW flags/control word; and a large, orthogonal instruction set with register, immediate, indirect, direct, indexed, relative and base addressing modes. Two variants shipped: the segmented Z8001 (23-bit addressing) and the non-segmented Z8002 (16-bit linear addresses). A pair of Z8002 CPUs form the main board of Namco's Pole Position (1982).
Architecture
- Registers. R0–R15, viewable as byte (RH/RL), word, long (RR pairs) and quad (RQ) groups; R15 is the usual stack pointer.
- Status. A 16-bit Flags and Control Word (FCW): C, Z, S, P/V, DA and H flags plus system/normal, segmentation and interrupt-enable control bits.
- Addressing. Register, immediate, indirect-register (@Rn), direct-address, indexed addr(Rn), relative and base — with a full 16-entry condition-code set on the jumps, calls and returns.
- Family. Z8001 (segmented, 8 MB), Z8002 (non-segmented, 64 KB), plus the Z8003/Z8004 virtual-memory parts and the Z8070 FPU / EPU coprocessors.
Machines
Emulators
| Emulator | Type | License | Site |
|---|---|---|---|
| Pole Position | online | Public domain | Website ↗ |