Chips › I/O & support › Serial & UART › Zilog Z80 SIO
Zilog Z80 SIO
1979
Zilog's Serial Input/Output controller, a Z80-family chip handling two channels of synchronous and asynchronous communication.
Reference & documentation
External technical references for programming Zilog Z80 SIO and for writing emulators.
| Resource | Type | Notes |
|---|---|---|
| Zilog Z80 SIO Product Specification (PS0183) ↗ | Datasheet | Official Zilog spec: modes, registers, timing, packages |
| Interfacing Z80 CPUs to the Peripheral Family ↗ | Datasheet | App note: bus, INTACK, wait-state and daisy-chain interfacing |
| Z80 Family Interrupt Structure ↗ | Interrupt list | IEI/IEO daisy-chain, vectors, RETI, mode 2 |
| Z80 SIO Product Specification (Feb 1980, bitsavers) ↗ | Pinout | Original spec with pin assignments and functions |
| Zilog Z80-SIO Technical Manual ↗ | Programming | Definitive manual: full WR/RR init sequences, protocols |
| LM80C: Z80 SIO and Serial Communication ↗ | Programming | Homebrew SIO+CTC setup, interrupt-driven receive walkthrough |
| SIO.ASM Z80 Serial Driver ↗ | Programming | Assembly RX/TX and baud-rate SIO/CTC init tables |
| CPCWiki: Z80-DART/Z80-SIO Chip ↗ | Reference | Emulator-oriented WR/RR bit-field tables and variants |
| Z80 Family CPU Peripherals Data Book ↗ | Reference | Combined SIO/PIO/CTC/DART peripheral electrical and timing data |
| MAME z80sio.cpp Emulation Source ↗ | Source | Reference implementation of register and interrupt behavior |
| Z80 SIO Emulation (Part 2) - Hackaday ↗ | Source | Emulating SIO register-select protocol and interrupt vector |