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DEC StrongARM
1996
DEC's high-performance 1996 ARM implementation, later sold to Intel, powering Acorn's Risc PC and many early handheld PDAs.
Emulators
| Emulator | Type | License | Site |
|---|---|---|---|
| RPCEmu | downloadable | GPL-2.0 | Website ↗ |
| Red Squirrel | downloadable | Freeware | Website ↗ |
| VirtualAcorn (VirtualRPC) | downloadable | Commercial | Website ↗ |
Reference & documentation
External technical references for programming DEC StrongARM and for writing emulators.
| Resource | Type | Notes |
|---|---|---|
| DEC StrongARM SA-110 Data Sheet v2.0 ↗ | Datasheet | Original DEC SA-110 datasheet, full technical spec |
| StrongARM SA-110 Brief Datasheet (278230) ↗ | Datasheet | Feature summary: microarchitecture, cache, signal lines |
| ARM Architecture Reference Manual (ARM ARM, DDI0100) ↗ | Instruction set | Canonical ARMv4/v5 opcode encodings and semantics |
| ARM7TDMI Technical Reference Manual (DDI0029G) ↗ | Instruction set | ARMv4T core: instruction encodings and cycle timing |
| SA-1100 Microprocessor Technical Reference Manual ↗ | Interrupt list | Interrupt controller and IRQ source assignments |
| SA-1100 Microprocessor Technical Reference Manual ↗ | Memory map | Full address space and register memory layout |
| DEC StrongARM SA-110 Data Sheet v2.0 ↗ | Pinout | Signal descriptions and package pin assignments |
| ARM7TDMI Instruction Set Reference ↗ | Programming | Concise per-instruction assembly programming reference |
| SA-110 Microprocessor Technical Reference Manual ↗ | Reference | Official SA-110 TRM: MMU, cache, boundary scan |
| StrongARM SA-1100 Specification Update (Errata) ↗ | Reference | Errata, clarifications, undocumented hardware behaviors |
| SingleStepTests / ARM7TDMI ↗ | Test suite | 20k JSON tests per encoding with cycle-accurate bus |