Chips › I/O & support › Custom & glue logic › Atari ST GLUE
Atari ST GLUE
1985
Atari ST's custom GLUE chip, generating system timing and address decoding that tied the ST's memory, video and I/O together.
Machines
Operating systems
Reference & documentation
External technical references for programming Atari ST GLUE and for writing emulators.
| Resource | Type | Notes |
|---|---|---|
| Atari ST Internals: hardware memory map ↗ | Datasheet | Full ST custom-chip and register memory map |
| Atari STE Hardware (Info-Coach / DrCoolZic) ↗ | Interrupt list | GLUE interrupt generation, IPL, MFPINT, IACK |
| Reverse-engineering the GLUE ASIC (Keli Hlodversson) ↗ | Memory map | GLUE address decoding, RAM/ROM ranges, GAMECART register |
| Atari ST Internals (full book PDF) ↗ | Pinout | GLUE chip pinout and signal descriptions |
| Atari STE Hardware architecture reference ↗ | Reference | GLUE role, clocks, bus arbitration, address decoding |
| How the Atari ST Core Works (MiST wiki) ↗ | Reference | IO-chip architecture, GLUE role, video timing |
| Recovering Atari ST ASIC designs (CHZ-Soft) ↗ | Schematic | Recovered original Atari GLUE/GSTMCU ASIC schematics and drawings |
| Translating GLUE schematics to Verilog (Keli) ↗ | Source | Verilog translation of GLUE schematics, simulation-verified |
| MiSTery: cycle-accurate Atari ST/STe FPGA core ↗ | Source | Cycle-accurate GLUE+MMU core from original schematics |
| Suska: VHDL open-source Atari ST(E) IP-core ↗ | Source | Open-source VHDL reconstruction starting from GLUE decoder |
| Recovered Atari GLUE ASIC netlists and test vectors ↗ | Test suite | Original netlists, simulation data and test vectors |