Chips › Processors › Console RISC processors › Hitachi SH-4

Hitachi SH-4

1998

Hitachi's 1998 32-bit RISC CPU with a fast vector FPU, the main processor of Sega's Dreamcast.

Machines

Sega Dreamcast

Emulators

EmulatorTypeLicenseSite
ChankastdownloadableFreewareWebsite ↗
DEmuldownloadableFreewareWebsite ↗
FlycastdownloadableGPL-2.0Website ↗
MakarondownloadableFreewareWebsite ↗
Sega DreamcastonlineOpen source · from-source SH-4 coreWebsite ↗
nullDCdownloadableMITWebsite ↗
redreamdownloadableFreewareWebsite ↗
reicastdownloadableGPL-2.0Website ↗

Reference & documentation

External technical references for programming Hitachi SH-4 and for writing emulators.

ResourceTypeNotes
SH-4 Hardware Manual (Hitachi, mc.pp.se PDF) ↗DatasheetSH7750 registers, bus, cache, timing specs
Renesas SH7750/S/R Hardware User's Manual ↗DatasheetLatest official hardware manual, all variants
SH7750 High-Performance RISC Engine (chipdb PDF) ↗DatasheetProduct datasheet, features and electrical overview
Renesas SH-4 Software Manual (PDF) ↗Instruction setOfficial opcode encodings, operations, cycle counts
SH-4 Programming Manual (mwk mirror PDF) ↗Instruction setFull instruction set with detailed encodings
metasm SH4 opcode table (opcodes.rb) ↗Instruction set200+ instructions with field masks
Dreamcast SH-4 Memory Map (Comstedt) ↗Memory mapLogical/physical address space and areas
SH-4 Hardware Manual (Hitachi, mc.pp.se PDF) ↗PinoutPin assignments and package information
Renesas SH-4 Software Manual (PDF) ↗ProgrammingCanonical CPU programming model reference
Dreamcast SH-4 CPU Overview (Comstedt) ↗ReferenceSH-4 core summary with manual downloads
metasm SH4 opcode table (opcodes.rb) ↗SourceMachine-readable 16-bit opcode encoding table
SingleStepTests SH4 conformance suite ↗Test suiteTomHarte-style JSON per-opcode CPU tests