Chips › Processors › Console RISC processors › Hitachi SH-2
Hitachi SH-2
1994
Hitachi's 1994 32-bit RISC CPU, used in dual form in the Sega Saturn and in the 32X add-on.
Machines
Emulators
| Emulator | Type | License | Site |
|---|---|---|---|
| BizHawk | downloadable | MIT | Website ↗ |
| Kronos | downloadable | GPL-2.0 | Website ↗ |
| Mednafen | downloadable | GPL-2.0 | Website ↗ |
| PicoDrive | downloadable | MAME | Website ↗ |
| SSF | downloadable | Freeware | Website ↗ |
| Sega 32X | online | Non-commercial (PicoDrive) | Website ↗ |
| Yabause | downloadable | GPL-2.0 | Website ↗ |
Reference & documentation
External technical references for programming Hitachi SH-2 and for writing emulators.
| Resource | Type | Notes |
|---|---|---|
| SH7604 Hardware Manual (ADE-602-085C) ↗ | Datasheet | 633-page SH-2 manual; registers, timing, electrical characteristics |
| SH7604 / HD6417604 Product Brief ↗ | Datasheet | Concise SH-2 specs, package and pinout summary |
| SH-1/SH-2 Programming Manual ↗ | Instruction set | Full opcode listing, encodings, cycle counts, flags |
| SH7604 Hardware Manual (ADE-602-085C) ↗ | Interrupt list | INTC vectors, priority registers, NMI and IRL sources |
| SH7604 Hardware Manual (ADE-602-085C) ↗ | Memory map | BSC address space, cache/uncached areas, DRAM/SRAM interfaces |
| SH7604 Hardware Manual (ADE-602-085C) ↗ | Pinout | Pin arrangement and pin function descriptions |
| SH-1/SH-2 Programming Manual ↗ | Programming | SuperH assembly, addressing modes, delayed branches, exceptions |
| SH-2E Software Manual (REJ09B0316) ↗ | Reference | SH-2E instruction detail including single-precision FPU |
| MAME SH-2 CPU core (sh2.cpp) ↗ | Source | Reference interpreter/DRC covering all SH-2 opcodes |
| PicoDrive SH-2 core (sh2.h) ↗ | Source | Compact 32X/Saturn SH-2 interpreter and DRC state |
| Ymir ymdasm SH-2 disassembler ↗ | Tool | CLI disassembler for big-endian 16-bit SH-2 opcodes |
| Ghidra SuperH SH-2 processor module ↗ | Tool | SLEIGH definitions for all SH-1/SH-2 instructions |