Chips › Processors › Motorola 6800 family › Hitachi HD6301
Hitachi HD6301
1983
Hitachi's 1980s enhanced 6801 microcontroller, a single-chip CPU with built-in RAM, timer and I/O used in embedded control and peripherals.
Machines
Emulators
| Emulator | Type | License | Site |
|---|---|---|---|
| Jape | online | Freeware | Website ↗ |
| Jape (Psion Organiser II) | online | Freeware | Website ↗ |
| Psion Organiser II LZ64 | online | Freeware | Website ↗ |
| Psiora | downloadable | GPL-3.0 | Website ↗ |
Reference & documentation
External technical references for programming Hitachi HD6301 and for writing emulators.
| Resource | Type | Notes |
|---|---|---|
| HD6301/HD6303 Series Handbook 1989 (Hitachi) ↗ | Datasheet | Canonical Hitachi databook; full PDF downloadable |
| HD6303 Instruction Set (alphabetical, opcodes + timing) ↗ | Instruction set | Every mnemonic with hex opcode, bytes, cycles, flags |
| HD6301 Undocumented Opcodes $12/$13 (addx) ↗ | Instruction set | Documents illegal opcodes used on Namco MCUs |
| HD6301V1 - NeoGeo Development Wiki ↗ | Memory map | Internal register and RAM/ROM address map |
| HD6303Y Datasheet (pinout, electrical, timing) ↗ | Pinout | Pin assignments, AC/DC characteristics, bus timing |
| HD6301V1 Programming Example - NeoGeo Wiki ↗ | Programming | Annotated init, SCI, interrupt-handler assembly |
| ISIS-II 6301 Cross Assembler User's Manual ↗ | Programming | Assembler directives, syntax, HD6301 instruction reference |
| HD6301/6303 Handbook PDF (Jaap's mirror) ↗ | Reference | Architecture, addressing modes, ports, timer, SCI |
| MAME m6801.cpp (HD6301/HD6303 CPU core) ↗ | Source | Reference emulator implementation of all HD6301 variants |
| Ghidra HD6301/HD6303 Support (PR #6314) ↗ | Source | SLEIGH disassembly spec derived from user's manual |