Chips › I/O & support › Custom & glue logic › MOS 906114 PLA
MOS 906114 PLA
1982
MOS Technology's 906114 Programmable Logic Array, generating the memory-banking and chip-select signals inside the Commodore 64.
Reference & documentation
External technical references for programming MOS 906114 PLA and for writing emulators.
| Resource | Type | Notes |
|---|---|---|
| C64 PLA Logic Equations (zimmers) ↗ | Datasheet | 82S100 datasheet plus Abel equations and JEDEC |
| C64 PLA JEDEC fuse map ↗ | Format | JEDEC file to burn 82S100 replacement |
| Codebase64: Memory Management ↗ | Memory map | Bank-switching modes via LORAM/HIRAM/CHAREN control lines |
| Bank Switching - C64-Wiki ↗ | Memory map | All 14 real PLA memory configurations explained |
| 906114-01 PLA pinout & datasheet ↗ | Pinout | 906114 pinout, function summary, chip photo |
| The C64 PLA Dissected (skoe) ↗ | Reference | Definitive transistor-level reverse engineering with logic equations |
| PLA (C64 chip) - C64-Wiki ↗ | Reference | Chip overview, 28-pin pinout, memory-map role |
| PLA20V8 build-it-yourself (freepascal) ↗ | Reference | GAL replacement with CUPL equations and timing |
| A Plethora of PLAs (breadbox64) ↗ | Reference | Survey of PLA replacements and timing constraints |
| pla-906114-1.c truth table generator ↗ | Source | C source: PLA equations to 64K truth table |